Άρθρα σε Περιοδικά
[J35] G. Hatzivasilis, I. Papaefstathiou and C. Manifavas, “SCOTRES: Secure Routing for IoT and CPS,” in IEEE Internet of Things Journal, vol. PP, no. 99, pp. 1-1.
doi: 10.1109/JIOT.2017.2752801 (Impact factor: 7.92)
[J34] K. Makantasis, A. Nikitakis, A. Doulamis, N. Doulamis and Y. Papaefstathiou, “Data-Driven Background Subtraction Algorithm for in-Camera Acceleration in Thermal Imagery,” in IEEE Transactions on Circuits and Systems for Video Technology, vol. PP, no. 99, pp. 1-1. doi: 10.1109/TCSVT.2017.2711259, (Impact factor: 3.59)
[J33] G. Hatzivasilis, K. Fysarakis, I. Papaefstathiou, C. Manifavas, “A review of lightweight block ciphers,” Journal of Cryptographic Engineering (JCEN), Springer, Available online 12 April 2017, doi:10.1007/s13389-017-0160-y.
[J32] Achilleas Tripolitsiotis, Nikolaos Prokas, Sarantis Kyritsis, Apostolos Dollas, Ioannis Papaefstathiou, and Panagiotis Partsinevelos, “Dronesourcing: a modular, expandable multi-sensor UAV platform for combined, real-time environmental monitoring”, International Journal Of Remote Sensing Vol 38, Issue 8-10
[J31] Kalaitzis, K.; Sotiriadis, E.; Papaefstathiou, I.; Dollas A., “Evaluation of External Memory Access Performance on a High-End FPGA Hybrid Computer”. Computation 2016, 4, 41.
[J30] G. Hatzivasilis, I. Papaefstathiou, D. Plexousakis, C. Manifavas, N. Papadakis, “AmbISPDM: Managing Embedded Systems in Ambient Environment and Disaster Mitigation Planning”, Applied Intelligence, Springer (2017), Available online 30 August 2017
[J29] N. Tampouratzis, P. Mattheakis, I. Papaefstathiou, “Accelerating Intercommunication in Highly Parallel Systems”, ACM Transactions on Architecture and Code Optimization, Vol 13, Issue 4, Article 40, December 2016
[J28] G. Hatzivasilis, G. Floros, I. Papaefstathiou, C. Manifavas, “Lightweight Authenticated Encryption for Embedded On-Chip Systems”, Information Security Journal: A Global Perspective, Taylor & Francis, vol25, issue 4-6, pp 151-161, August 2016
[J27] K. Fysarakis, O. Sultatos, C. Manifavas, I. Papaefstathiou, I. Askoxylakis, “XSACd: Cross-domain Resource Sharing & Access Control for Smart Environments”, Future Generation Computer Systems, Elsevier, Available online 7 June 2016.
[J26] G. Hatzivasilis, I. Papaefstathiou and C. Manifavas, “Software Security, Privacy, and Dependability: Metrics and Measurement” IEEE Software, vol. 33, no. 4, pp. 46-54, July-Aug. 2016.
[J25] Manifavas, C., Hatzivasilis, G., Fysarakis, K., and Papaefstathiou, Y. “A survey of lightweight stream ciphers for embedded systems”. Security Comm. Networks, 9: 1226–1246, 2016.
[J24] K. Fysarakis, D. Mylonakis, C. Manifavas and I. Papaefstathiou, “Node.DPWS: Efficient Web Services for the Internet of Things” IEEE Software, vol. 33, no. 3, pp. 60-67, May-June 2016.
[J23] K. Fysarakis, G. Hatzivasilis, C. Manifavas and I. Papaefstathiou, “RtVMF: A Secure Real-Time Vehicle Management Framework” IEEE Pervasive Computing, vol. 15, no. 1, pp. 22-30, Jan.-Mar. 2016. (In top 5 list among all Security papers in 2016 in the MENA region)
[J22] Manifavas, C, Fysarakis, K, Papanikolaou, A, and Papaefstathiou, I, “Embedded Systems Security: A Survey of EU Research Efforts” Security Comm. Networks, 8, 2016–2036, 2015.
[J21] D. Pnevmatikatos, , b, E. Vansteenkistec, K. Papadimitriou, T. Becker, P. Böhm, A. Brokalakis, K. Bruneel, C. Ciobanu, T. Davidson, G. Gaydadjiev, K. Heyse, W.Luk, X. Niub, I. Papaefstathiou, D. Paug, O. Pellf, C. Pilato, M.D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman, E. Vansteenkiste “FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration” Elsevier, Microprocessors and Microsystems Volume 37, Issue 8
[J20] T. Theocharides, A. Dollas, I. Papaefstathiou, E. Sotiriades, V.J. Promponas, G. Chrysos, A. Papadopoulos, I. Kirmitzoglou, G. Petihakis, C. Rousopoulos, K. Pramataris, J. Lagnel, “Reconfiguring the Bioinformatics Computational Spectrum: Challenges and Opportunities of FPGA-Based Bionformatics acceleration platforms”, IEEE Design & Test of Computers, Volume 31, Issue 1
[J19] Luciano Lavagno, Mihai T. Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schäfer, “HEAP: A Highly Efficient Adaptive multi-Processor framework”, Elsevier Microprocessors and Microsystems, Volume 37, Issue 8, ISSN 0141-9331
[J18] A. Nikitakis, S. Papaioannou, I. Papaefstathiou, “A Novel Low-power Embedded Object Recognition System working at multi-frames per second”, ACM Transactions on Embedded Computing Systems, Vol 11, No 2, June 2013 (Best Paper Award ESTIMedia 2012)
[J17] G. Chrysos, P. Dagritzikos, I. Papaefstathiou, A. Dollas, “HC-CART: A Parallel System Implementation of Data Mining Classification and Regression Tree (CART) algorithm on a multi-FPGA system”, ACM Transactions on Architecture and Code Optimization, Vol. 9, No. 4, Article 51, January 2013
[J16] P. Mattheakis, I. Papaefstathiou “Significantly Reducing MPI Intercommunication Latency and Power Overhead in Both Embedded and HPC Systems”, ACM Transactions on Architecture and Code Optimization, Vol. 9, No. 4, Article 51, January 2013
[J15] P. Karkazis, P. Trakadas, H.C. Leligou, L. Sarakis, I. Papaefstathiou, T. Zahariadis, “Evaluating routing metric composition approaches for QoS differentiation in low power and lossy networks”, Wireless Networks, Springer, Published On-line December 2012.
[J14] Th. Zahariadis, H. Leligou, P. Karkazis, P. Trakadas, I. Papaefstathiou, Ch. Vangelatos, L. Besson, “Design and implementation of a Trust-Aware Routing Protocol For Large WSNs” International Journal of Network Security & its Applications (IJNSA, Vol.2, No.3, July 2010, pp. 52-68
[J13] D. Katzourakis, I. Papaefstathiou, M. Lagoudakis, “Open-Source Experimental Platform for Real-Time Data Fusion”, IEEE Transactions on Instrumentation and Measurement, vol. 59, no. 9, pp. 2303-2314, 2010
[J12] K. Papadopoulos, I. Papaefstathiou, “Titan-R: A Reconfigurable hardware implementation of a high-speed compressor/ decompressor” ACM Transactions on Reconfigurable Technology and Systems (TRETS) Volume 3 , Issue 2 (May 2010)
[J11] I. Mavroidis, I Papaefstathiou, “Accelerating Emulation and Providing Full Chip Observability and Controllability at Run-Time” IEEE Design & Test of Computers, November/December 2009 (vol. 26 no. 6), pp. 84-94
[J10] D. Simos, Ι. Papaefstathiou, M. Katevenis, “Building an FoC Using Large, Buffered CrossbarCores”, IEEE Design & Test (D&T) Nov/Dec 2008
[J9] K. Vlachos, T. Orphanoudakis, I. Papaefstathiou, N. Nikolaou, D. Pnevmatikatos, G. Konstantoulakis, J.A. Sanchez-P, “Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units”, Elsevier Journal on Microprocessors and Microsystems, Volume 31, Issue 3, May 2007, pages 188-199
[J8] I. Papaefstathiou, “Titan II : An IPComp Processor for 10Gbit/sec network”, IEEE Design & Test (D&T), Nov. 2004
[J7] I. Papaefstathiou, S. Perissakis, T. Orphanoudakis, N. Nikolaou, G. Kornaros, , D. Pnevmatikatos, G. Konstantoulakis, N. Zervos “PRO3: A Hydrid NPU Architecture”, IEEE Micro, special Issue on Network Processors, Sep/Oct 2004
[J6] Ι. Papaefstathiou, N. Nikolaou, B. Doshi, E. Grosse, “Network Processors for Future High-End Systems and Applications”, IEEE Micro, special Issue on Network Processors, Sep/Oct 2004
[J5] Ι. Papaefstathiou, V. Papaefstathiou and C. Sotiriou, “Design-Space Exploration of the most widely used Cryptography Algorithms”, Elsevier Journal on Microprocessors and Microsystems, special issue on Secure Computing Platforms, Volume: 28, Issue:8, 11 September 2004, Pages 561-571
[J4] A. Nikologiannis, I. Papaefstathiou, G.Kornaros, C. Kachris, “An FPGA-based Queue Management System for High Speed Networking Devices”, Elsevier Journal on “Microprocessors and Microsystems”, special issue on FPGAs, Volume 28, Issues 5-6 , 2 August 2004, Pages 223-236
[J3] Ι. Papaefstathiou, “Low-level Hardware Compression for Multi-Gigabit Networks”, Journal of Circuits, Systems and Computers, Vol. 13, No. 6 (2004), Pages 1307-1319.
[J2] I. Papaefstathiou, K. Vlachos, N. Nikolaou and V.B. Lawrence, “Packet processing acceleration with a 3-stage re-configurable pipeline engine”, IEEE Communications Letters, Volume: 8, Issue: 3, March 2004
[J1] I. Papaefstathiou, C. Manifavas, “Evaluation of Micropayment Transaction Cost”, Journal of Electronic Commerce Research, Volume : 5, Number : 2, 2004, Pages 99-114,
Άρθρα σε Συνέδρια
[C83] Andreas Brokalakis, Nikolaos Tampouratzis, Antonios Nikitakis, Ioannis Papaefstathiou, Stamatis Andrianakis, Apostolos Dollas, “An Open-Source Extendable, Highly-Accurate and Security Aware CPS Simulator”, 13th International Conference on Distributed Computing in Sensor Systems (DCOSS 2017), Ottawa, Canada, June 5-7, 2017.
[C82] Emmanouil Kousanakis, Apostolos Dollas, Euripides Sotiriades, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Athanasia Papoutsiy, Panagiotis C. Petrantonakisy, Panayiota Poiraziy, Spyridon Chavlis and George Kastellakis, “An Architecture for the Acceleration of a Hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based Processor”, 25th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2017), April 30 – May 2, Napa, CA, USA (acceptance rate 18%)
[C81] K. Fysarakis, O. Soultatos, I. Askoxylakis, C. Manifavas, I. Papaefstathiou and V. Katos, “Which IoT Protocol? Comparing standardized approaches over a common M2M application”, 2016 IEEE Global Communications Conference (GLOBECOM 2016), Washington, DC, USA, December 4-8, 2016.
[C80] I. Papaefstathiou, “IoT design course using open-source tools” 2016 IEEE Global Engineering Education Conference (EDUCON), Abu Dhabi, 2016.
[C79] Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino, “ECOSCALE: Reconfigurable computing and runtime system for future exascale systems” 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 14-18 Dresden, 2016 (acceptance rate 24%)
[C78] A. Nikitakis, I. Papaefstathiou, K. Makantasis and A. Doulamis, “A novel background subtraction scheme for in-camera acceleration in thermal imagery” 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 14-18 Dresden, 2016,
[C77] A. Nikitakis and I. Papaefstathiou, “Highly efficient reconfigurable parallel graph cuts for embedded vision” 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 14-18 March, 2016. (acceptance rate 24%)
[C76] G. Hatzivasilis, I. Papaefstathiou and C. Manifavas, “ModConTR: A modular and configurable trust and reputation-based system for secure routing in ad-hoc networks”, IEEE 11th ACS Int. Conf. on Computer Systems and Applications (AICCSA 2014), Doha, Qatar, 10-13 Nov., 2014
[C75] K. Fysarakis, K. Rantos, C. Manifavas, O. Sultatos and I. Papaefstathiou, “Policy-based Access Control for DPWS-enabled Ubiquitous Devices”, 19th IEEE Int. Conference on Emerging Technologies and Factory Automation (ETFA 2014), Barcelona, Spain, September 16-19, 2014
[C74] Athanasios Stratikopoulos, Grigorios Chrysos, Ioannis Papaefstathiou and Apostolos Dollas. “HPC-gSpan: An FPGA-based Parallel System for Frequent Subgraph Mining Problem”, 24th International Conference on Field Programmable Logic and Applications (FPL), September 2 – 4, 2014 Munich, Germany. (acceptance rate 29%)
[C73] C. Manifavas, K. Fysarakis, K. Rantos, K. Kagiambakis and I. Papaefstathiou, “Policy-based Access Control for Body Sensor Nodes”, IFIP Workshop in Information Security Theory and Practice (WISTP 2014), Heraklion, Crete, Greece, 30 June – 2 July, 2014, LNCS 8501, Springer 2014.
[C72] Panagiotis Karkazis, Ioannis Papaefstathiou, Lambros Sarakis, Theodore Zahariadis, Terpsichori-Helen Velivassaki, Dimitrios Bargiotas, “Evaluation of RPL with a Transmission Count-Efficient and Trust-Aware Routing Metric”, IEEE International Conference on Communication (ICC), Jun 10-14, 2014, Syndey, Australia.
[C71] Hatzivasilis, G.; Papaefstathiou, I.; Manifavas, C.; Papadakis, N., “A Reasoning System for Composition Verification and Security Validation” 2014 6th International Conference on New Technologies, Mobility and Security (NTMS), March 30 2014-April 2 2014, Dubai. U.A.E.
[C70] Nikitakis, A.; Paganos, T.; Papaefstathiou, I., “A novel embedded system for vision tracking” Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, 24-28 March 2014, Dresden, Germany
[C69] K. Fysarakis, C. Manifavas, I. Papaefstathiou and A. Adamopoulos, “A lightweight anonymity & location privacy service” IEEE International Symposium on Signal Processing and Information Technology, Athens, 2013
[C68] G. Raptis, I. Papaefstathiou, K. Georgopoulos and C. Manifavas, “A novel highly flexible network multi-processor optimised for reconfigurable devices” AFRICON, 2013, Pointe-Aux-Piments, 2013
[C67] D. Tsiamasiotis, I. Papaefstathiou and C. Manifavas, “Highly parallel implementation of Sphinx-3 voice recognition algorithm” AFRICON, 2013, Pointe-Aux-Piments
[C66] K. Rantos, A. Papanikolaou, C. Manifavas and I. Papaefstathiou, “IPv6 security for low power and lossy networks” Wireless Days (WD), 2013 IFIP, Valencia, 2013, pp. 1-8.
[C65] Panos Papantonakis, Charalampos Manifavas, Dionisios Pnevmatikatos, Ioannis Papaefstathiou, “Fast, FPGA-based Rainbow Table Creation for Attacking Encrypted Mobile Communications”, IEEE International Conference on Field Programmable Logic and Applications (FPL), Sept. 2-4, 2013, Porto, Portugal, (acceptance rate 28%)
[C64] T. Tzanoudakis, I. Papaefstathiou and C. Manifavas, “Parallelizing bioinformatics and security applications on a low-cost multi-core system” Computer Systems and Applications (AICCSA), 2013 ACS International Conference on, Ifrane, 2013.
[C63] Maria Kalenderi, Dionisios N. Pnevmatikatos, Ioannis Papaefstathiou, Charalampos Manifavas “ Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGAs”. IEEE International Conference on Field Programmable Logic and Applications (FPL), 2012, Aug 29-21, Oslo, Norway (acceptance rate 25%)
[C62] Dionisios N. Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Karel Bruneel, Georgi Gaydadjiev, W. Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, O. Pell, Christian Pilato, M. Robart, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman: “FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration”. 15th Euromicro Conference on Digital System Design, September 5-8, 2012, Cesme, Izmir, Turkey
[C61] Luciano Lavagno, Mihai T. Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schäfer: “HEAP: A Highly Efficient Adaptive Multi-processor Framework”. 15th Euromicro Conference on Digital System Design, September 5-8, 2012, Cesme, Izmir, Turkey
[C60] Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Mihai Lazarescu, Eduardo de la Torre, “FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels”, 15th Euromicro Conference on Digital System Design, September 5-8, 2012, Cesme, Izmir, Turkey
[C59] Andreas Brokalakis, Ioannis Papaefstathiou. “Using hardware-based forward error correction to reduce the overall energy consumption of WSNs”. 2012 IEEE Wireless Communications and Networking Conference, WCNC 2012, Paris, France, April 1-4, 2012.
[C58] Georgios-Grigorios Mplemenos, Ioannis Papaefstathiou, “Fast and power-efficient hardware implementation of a routing scheme for WSNs” 2012 IEEE Wireless Communications and Networking Conference, WCNC 2012, Paris, France, April 1-4, 2012.
[C57] G. Chatziparaskevas, A. Brokalakis, I. Papaefstathiou, “An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes”, IEEE Design, Automation and Test Europe Conference 2012 (DATE 2012), March 8-12, Dresden, Germany (acceptance rate 22%).
[C56] D. Meidanis, K. Georgopoulos, I. Papaefstathiou, “FPGA Power Consumption Measurements and Estimations Under Different Implementation Parameters”, IEEE International Conference on Field Programmable Technology 2011 (FPT’11), December 7th -10th New Delhi, India.
[C55] P. Dagritzikos, G. Chrysos, I. Papaefstathiou, A. Dollas “Novel and Highly Efficient Reconfigurable Implementation of Data Mining Classification Tree” IEEE International Conference on Field Programmable Logic and Applications (FPL), 2011, Sept 3- 6, Chania, Greece, (Ποσοστό αποδοχής εργασιών 23%)
[C54] G. Mplemenos, K. Papadopoulos, A. Brokalakis, I. Papaefstathiou, “RESENSE: An Innovative, Reconfigurable, Powerful and Energy Efficient WSN Node”, IEEE International Conference on Communications 2011 (ICC-2011) June 5-9 , Kyoto, Japan (acceptance rate 36%)
[C53] M. Lakka, G. Chrysos, I. Papaefstathiou, A. Dollas, “Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic”, 19th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2011), May 1-3, Salt Lake City, Utah, U.S.A. (acceptance rate 16%)
[C52] N Chrysanthou, G Chrysos, E Sotiriades, I Papaefstathiou, “Parallel Accelerators For GlimmerHMM Bioinformatics Algorithm”, IEEE Design, Automation and Test Europe Conference 2011 (DATE 2011), 14-18 March 2011, Grenoble, France (acceptance rate 24%).
[C51] G. Mplemenos, K. Papadopoulos, I. Papaefstathiou “Using Reconfigurable Hardware Devices in WSNs for Reducing the Energy Consumption of Routing and Security Tasks”, IEEE GLOBECOM 2010, December 6-10, Maimi, USA (acceptance rate 31%).
[C50] K. Theocharoulis, C. Manifavas, I. Papaefstathiou, “Implementing Rainbow Tables in High-end FPGAs for Super-fast Password Cracking”, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2010, Aug 31- Sept 2, Rome, (acceptance rate 23%)
[C49] D. Mpouris, A. Nikitakis, I. Papaefstathiou, “Fast and Efficient FPGA-based Feature Detection employing the SURF algorithm”, 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), May 2-4, Charlotte, North Carolina, U.S.A. (acceptance rate 17.4%)
[C48] G. Chrysos, I. Papaefstathiou, “Heavily Reducing WSNs’ Energy Consumption by Employing Hardware-Based Compression”, IEEE ADHOC-NOW 2009, Sept. 20-23 Murcia, Spain, (acceptance rate 27%)
[C47] K. Kontos, D. Pnevmatikatos, I. Papaefstathiou, “Design Space Exploration of Reconfigurable Systems for Calculating Flying Object’s Optimal Noise Reduction Paths”, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2009, Aug 31- Sept 2, Prague, Czech Republic, (Ποσοστό αποδοχής εργασιών 23%)
[C46] I. Sotiropoulos, I. Papaefstathiou, “A fast parallel matrix multiplication reconfigurable unit utilized in face recognition systems”, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2009, Aug 31- Sept 2, Prague, Czech Republic, (acceptance rate 23%)
[C45] Charalampos Effraimidis, Kyprianos Papadimitriou, Apostolos Dollas, Ioannis Papaefstathiou, “A Self-Reconfiguring architecture supporting multiple objective functions in genetic algorithms”, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2009, Aug 31- Sept 2, Prague, Czech Republic
[C44] Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou, Apostolos Dollas, “A FPGA-based Coprocessor for Gene finding using Interpolated Markov Model (IMM)”, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2009, Aug 31- Sept 2, Prague, Czech Republic
[C43] K. Vavouras, K. Papadimitriou, I. Papaefstathiou, “High-speed FPGA-based Implementations of a Genetic Algorithm”, International Symposium on Systems, Architectures, MOdeling and imulation, SAMOS IX, Samos, Greece, July 20-23, 2009
[C42] Michalis Platsis, Ioannis Papaefstathiou and Dimitrios Meintanis
“Design and Implementation of an UWB Digital Transmitter Based on the Multiband OFDM Physical Layer Proposal”, 20th IEEE/IFIP International Symposium on
Rapid System Prototyping, RSP’09, June 23-26, 2009 Paris, France
[C41] E. Ladis, I. Papaefstathiou, R. Marchesani, K. Tuinenbereijer, P. Langendorfer, T. Zahariadis, H.C. Leligou, L. Redondo, T. Riesgo, P. Kannegiesser, M. Berekovic, C.J.M. van Rijin, “Secure Mobile Visual Sensor Networks Architecture”, IEEE SECON 2009, 22-26 June 2009, Invited paper
[C40] K. Theocharoulis, C. Manifavas, I. Papaefstathiou, “High-End Reconfigurable Systems for fast Password Cracking”, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2009, April 5-7, Napa California USA.
[C39] Panagiotis Afratis, Constantinos Galanakis, Euripides Sotiriades, Georgios-Grigorios Mplemenos, Grigorios Chrysos, Yiannis Papaefstathiou, Dionisios Pnevmatikatos: “Design and Implementation of a Database Filter for BLAST Acceleration”, In Proceedings, Design, Automation and Test Europe, 20-24 April 2009, Nice, France (acceptance rate 22%).
[C38] D. Meidanis, I. Papaefstathiou, “On the Power Consumption of security algorithms employed in wireless networks”, 6th Annual IEEE Consumer Communications & Networking Conference (CCNC 2009) 10 – 13 January 2009 Las Vegas, Nevada. USA (acceptance rate 31%)
[C37] I Mavroidis, I. Papaefstathiou, “Accelerating Hardware Simulation: Testbench Code Emulation”, IEEE International Conference on Field Programmable Technology 2008 (FPT’08), December 7th -10th Taipei, Taiwan (acceptance rate 22%).
[C36] Dimitris Theodoropoulos, Ioannis Papaefstathiou, Dionisios Pnevmatikatos, “CCproc: An Efficient Cryptographic Coprocessor”, 16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2008), October 13-15, 2008 Rhodes Island, Greece
[C35] A. Nikitakis, I. Papaefstathiou, “A memory-efficient FPGA-based classification engine”, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2008, April 13-15, Palo Alto USA (acceptance rate 20%)
[C34] K. Papadopoulos, I. Papaefstathiou, “Titan-R: A Reconfigurable hardware implementation of a high-speed compressor”, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2008, April 13-15, Palo Alto, USA (acceptance rate 20%)
[C33] G. Mplemenos, I. Papaefstathiou, “MPLEM: An FPGA Based Multiprocessor System for BLAST Algorithm”, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2008, Poster, April 13-15, Palo Alto, USA
[C32] A. Nikitakis, I. Papafefstathiou, “A Multi Gigabit FPGA-based 5-tuple classification system”, IEEE International Conference on Communications 2008, ICC-2008, May 19-23, Beijing, China (acceptance rate 36%)
[C31] D. Meintanis, I. Papaefstathiou, “An efficient FPGA-based implementation of Pollard’s (rho-1) factorization algorithm”, Poster, International Conference on Field-Programmable Technology 2007 (ICFPT’07), December 12-14, 2007 Kokurakita, Kitakyushu, Japan.
[C30] Dimopoulos, V.; Papaefstathiou, I.; Pnevmatikatos, D., “A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems” Embedded Computer Systems: Architectures, Modeling and Simulation, 2007. IC-SAMOS 2007. International Conference on , vol., no., pp.186,193, 16-19 July 2007
[C29] I. Papaefstathiou, V. Papaefstathiou, “Memory-Efficient 5D Packet Classification at 40Gbps”, IEEE INFOCOM 2007, May 6-12, Anchorage, Alaska, U.S.A (Ποσοστό αποδοχής εργασιών 18%).
[C28] I. Mavroidis, D. Pnevmatikatos, I. Papaefstathiou, “FPGA-Based Implementation of Symmetrical 2-Opt Moves for the Traveling Salesman Problem”, IEEE Symposium on Field-Programmable Custom Computing Machines, April 23-25, 2007, Napa Valley, California, U.S.A (acceptance rate 21%).
[C27] G. Kornaros, I. Papaefstathiou, D. Pnevmatikatos, “Dynamic Software-Assisted Monitoring of On-Chip Interconnects”, Workshop on Diagnostic Services in Network-on-Chips, IEEE Design Automation & Test in Europe 2007 (DATE 2007), April 16-20, Nice, France (Acceptance Rate in workshop 18%).
[C26] I. Mavroidis, I. Papaefstathiou, “Efficient Testbench Code Synthesis for a Hardware Emulator System”, IEEE Design Automation & Test in Europe 2007 (DATE 2007), April 16-20, Nice, France (Acceptance Rate 22%).
[C25] I. Papaefstathiou, G. Kornaros, N. Chrysos, “Using Buffered Crossbars for Chip Interconnection”, ACM/IEEE Great Lakes Symposium on VLSI 2007 (GLSVLSI 2007), March 11-14, Stresa, Italy (Acceptance Rate 21%) .
[C24] I. Papaefstathiou, V. Papaefstathiou, “An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks”, IEEE International Conference on Communication 2006, (ICC 2006), June 11-15 2006, Istanbul, Turkey (Acceptance Rate 34%).
[C23] V. Papaefstathiou, I. Papaefstathiou, “A Hardware-Engine for Layer-2 classification in low-storage, ultra-high bandwidth environments”, IEEE Design Automation & Test in Europe (DATE 2006), March 6-10, Munich, Germany (Acceptance Rate 21%).
[C22] V. Papaefstathiou, I. Papaefstathiou, “A Memory-Efficient, 100Gb/sec MAC Classification machine”, 30th Annual IEEE Conference on Local Computer Networks (LCN), November 15-17 2005, Sydney, Australia (Acceptance Rate 26.4%).
[C21] Aristides Efthymiou, Jim D. Garside and Ioannis Papaefstathiou “A low power processor architecture optimized for wireless devices”, 16th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2005), July 23 – 25, 2005, Samos, Greece
[C20] I. Papaefstathiou, T. Orphanoudakis, G. Kornaros, C. Kachris, I. Mavroidis, A. Nikologiannis, “Queue Management in Network Processors“ IEEE Design Automation & Test in Europe (DATE 2005), March 7-11, Munich, Germany (Acceptance Rate 21%).
[C19] Manolis Katevenis, Georgios Passas, Dimitrios Simos, Ioannis Papaefstathiou & Nikos Chrysos, “Variable Packet Size Buffered Crossbar (CICQ) Switches”, 2004 IEEE International Conference on Communications (ICC 2004), June 20-24, Paris, France (Acceptance Rate 29%).
[C18] I. Papaefstathiou, G. Kornaros, N. Zervos “Software processing performance in network processors”, IEEE Design Automation & Test in Europe (DATE 2004), February 16-20, Paris, France (Acceptance Rate 24%).
[C17] C. Sotiriou, I. Papaefstathiou, “A Design-Space Exploration of α Cryptography Algorithm”, 10th IEEE International Conference on Electronics, Circuits and Systems, (ICECS2003) , December 14 – 17, 2003, Sharja, U.A.E.
[C16] N. Mouratidis, G. Lykakis, A. Tavoularis, A. Kostopoulos, F. Petreas, D. Economou, A. Manousaridis, V. Vlaggoulis, Y. Papaefstathiou, Ch. Georgopoulos, G. Konstantoulakis, “Convergence Processor: Standard and Custom IP in an Innovative SoC Design for Broadband Residential Applications”, IIIS International Conference on Computer, Communication and Control Technologies (CCCT’03), July 31, August 1-2, 2003, Orlando, Florida, U.S.A. , Best paper session award
[C15] G. Kornaros, I. Papaefstathiou, “An Innovative Resource Management Scheme for Multi-Gigabit Networking Systems”, 6th IEEE International Conference on High Speed Networks and Multimedia Communications (HSNMC’03), July 23-25, 2003 Estoril, Portugal.
[C14] G. Kornaros, T. Orphanoudakis, I. Papaefstathiou, “GFS: An Efficient Implementation of Fair Scheduling for multi-Gigabit Packet Networks”, 14th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2003), June 24-26, 2003, Hague, The Netherlands.
[C13] G. Kornaros, I. Papaefstathiou, A. Nikologiannis, N.Zervos, “A Fully-Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit rates”, 40th IEEE/ACM Design Automation Conference (DAC), June 2-6, 2003, Anaheim, California, U.S.A. (Acceptance Rate 24%).
[C12] G. Kornaros, T. Orphanoudakis, I. Papaefstathiou, “Active Flow Identifiers for scalable, QoS scheduling in 10-Gbps network processors”, 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), May 25 – 28, 2003, Bangkok, Thailand.
[C11] I. Papaefstathiou, H.-C. Leligou, Th. Orphanoudakis, G. Kornaros, N. Zervos, G. Konstantoulakis, “An innovative scheduling scheme for high speed network processors”, IEEE International Symposium on Circuits and Systems (ISCAS 2003), May 25 – 28, 2003, Bangkok, Thailand.
[C10] T. Orphanoudakis, G. Kornaros, H.-C. Leligou, I. Papaefstathiou, S. Perissakis, N.Zervos, “Scheduling components for multi-gigabit network SoCs”, 2003 SPIE First International Symposium on Microtechnologies for the New Millennium 2003, 19-21 May 2003, Canary Islands, Spain.
[C9] Ι.Papaefstathiou, “Titan II : An IPComp Processor for 10Gbit/sec networks”, IEEE Computer Society Annual Symposium On VLSI Feb 20-21,2003, Tampa, USA. (Acceptance Rate 29%)
[C8] I. Papaefstathiou, C. Sotiriou, “Read, Use, Simulate, Experiment and Build : An Integrated Approach for Teaching Computer Architecture” , 8th Workshop on Computer Architecture Education (WCAE 2002), 29th International Symposium on Computer Architecture (ISCA 2002), Anchorage, Alaska, USA, 26 May 2002.
[C7] I. Papaefstathiou, “An Ultra High-Speed Compressor for Packet Networks” , 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2001), Valetta, Malta, 2-6 Sept. 2001.
[C6] I. Papaefstathiou, “A complete framework for on-line Compression of ATM streams“, IEEE/IEE International Conference on Telecommunications 2000 (ICT 2000), Acapulco, Mexico, 22-25 May 2000.
[C5] I. Papaefstathiou, “Measurement based Connection Admission Control algorithm for ATM networks that use low level compression“, 7th International Conference on Intelligence in Services and Networks, IS&N 2000, Lecture Notes in Computer Science n. 1774, pp. 138-146,Athens, Greece, 25-28 February 2000.
[C4] I.Papaefstathiou, Brown A., Simer J., Sobel D., Sutaria J., Wang S. Y., Blackwell T., Smith M., Yang W, “An IRAM-Based Architecture for a Single-Chip ATM Switch“, 6th IEEE International Conference on Electronics, Circuits and Systems (ICECS ’99), Paphos, Cyprus, 5-8 September 1999.
[C3] I. Papaefstathiou, “Compressing ATM streams on-line“, 1999 IEEE Data Compression Conference (DCC’99), Utah, USA, 29-31 March 1999.
[C2] I. Papaefstathiou, “Accelerating ATM : On-line compression of ATM streams“, 18th IEEE International Performance, Computing, and Communications Conference (IPCCC’99), Phoenix, Arizona, USA, 10-12 February 1999.
[C1] Brown, A., D. Chian, N. Mehta, I. Papaefstathiou, J. Simer, T. Blackwell, M. Smith, W. Yang, “Using MML to Simulate Multiple Dual-Ported SRAMs: Parallel Routing Lookups in an ATM Switch Controller“. 1997 Workshop on Mixing Logic and DRAM, International Symposium of Computer Architecture (ISCA ’97), Denver, Colorado, USA, 1 June 1997.
Κεφάλαια σε Βιβλία
[Β3] I. Papaefstathiou, C. Manifavas, Book Chapter 51, “Security in Ad Hoc Wireless Sensor Networks”, in Security in Computing and Networking Systems: The State-of-the-Art, Editors: William McQuay and Waleed W. Smari, Willey, October 2009
[Β2] G.Kornaros, D.Pnevmatikatos, and I.Papaefstathiou, “Monitoring Services for Networks-on-Chip”, Book Chapter 8, in “Networks-on-Chips: Theory and Practice” Editors: Fayez Gebali, Haytham Elmiligi, and M. Watheq El-Kharashi, CRC Press, in print March 2009.
[Β1] Th. Zahariadis. P. Trakadas, H. Leligou, K. Papadopoulos, E. Ladis, Ch. Tselikis, Ch. Vangelatos, L. Besson, J. Manner, M. Loupis, F. Alvarez, I. Papaefstathiou, “Securing Wireless sensor networks towards a trusted “Internet of Things””, Towards the Future Internet, G. Tselentis et. Al. (eds.), IOS Press (2009), doi: 10.3233/978-1-60750-007-0-47, σελ. 47-56.
Τεχνικές Αναφορές
[Τ3] I. Papaefstathiou, “Increasing packet network bandwidth through low level compression“, Ph.D. Thesis, Computer Lab, University of Cambridge, January 2001.
[Τ2] Brown A., I. Papaefstathiou, J. Simer, D. Sobel, J. Sutaria, S. Wang, T. Blackwell, M. Smith, W. Yang, “An IRAM-Based Architecture for a Single-Chip ATM Switch“, Technical Report TR-07-97, Center for Research in Computing Technology, Harvard University, 1997.
[Τ1] I. Papaefstathiou, “A behavioral model of ATLAS I (ATm multi-LAne Switch I) and the supporting modules for providing the input ATM traffic to ATLAS I and to the behavioral model(BeSwitch), and for checking the outputs of the two switches“, Διπλωματική Εργασία, Επόπτης: Καθηγητής Μ. Κατεβαίνης, Τμήμα Επιστήμης Υπολογιστών, Πανεπιστήμιο Κρήτης, Ηράκλειο, Μάϊος 1995.
